1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices, and particularly to a semiconductor integrated circuit device using BiCMOS technology.
2. Description of the Background Art
The BiMOS is a kind of circuit structure system in which a bipolar element and a MOS element are mixedly provided on the same chip, and is LSI technology in which a bipolar IC performing analog processes and an MOS IC performing digital processes with low consumption power are provided mixedly on the same chip.
The bipolar IC has an advantage that it can process high frequency signals and operate at high speed because it can perform analog processings with high accuracy and has large current driving capability. On the other hand, however, it has a disadvantage that the input impedance is low and consumption power is large. On the other hand, MOS IC has an advantage that the integrity level and input impedance are high but has a disadvantage that it is not suitable for analog processings.
Accordingly, a circuit configuration method, the BiMOS has been devised in order to realize semiconductor integrated circuit devices having advantages of both of bipolar IC and MOS IC. In order to make the most of strong points of both of the bipolar IC and the MOS IC, in a semiconductor integrated circuit device of BiMOS structure, a circuit portion for outputting TTL level signals includes a bipolar element and a MOS element, for example.
In the specification and drawings, N1-N80 denote N-channel MOS field effect transistors (NMOS transistors), and P1-P35, P61-P74 denote P-channel MOS field effect transistors (PMOS transistors). Also, B1-B22 denote NPN-type bipolar transistors.
(1) Schematic structure of the entirety of conventional SRAM (FIG. 45)
FIG. 45 is a block diagram illustrating a schematic structure of a conventional general SRAM (Static Random Access Memory) using the BiMOS technology.
In a memory cell array 51, a plurality of word lines and a plurality of bit line pairs are arranged intersecting one another and memory cells are provided at intersections thereof.
A row address buffer 52 applies row address signals X0-X7 externally supplied to a row decoder 53. Row decoder 53 selects one word line inside memory cell array 51 in response to a row address signal. A column address buffer 55 applies column address signals Y0-Y6 provided from outside to a column decoder 56. Column decoder 56 selects one bit line pair inside memory cell array 51 in response to a column address signal. Thus, a memory cell provided at an intersection of the selected word line and the selected bit line pair is selected. Data is written into the selected memory cell, or data stored in that memory cell is read out.
When both of a write enable signal WE and a chip select signal CS provided to a R/W control circuit 62 from outside attain "L", data writing operation is performed. At this time, input data to be written is applied to an input pin DQ. The input data is applied to a write driver 61 through a data input/output buffer 59 and R/W control circuit 62 and written into a selected memory cell inside memory cell array 51. When the writing operation is finished, bit line pairs inside memory cell array 51 are charged to a predetermined potential by a bit line load circuit 60.
When a write enable WE attains "H", data reading operation is performed. Data stored in a selected memory cell inside memory cell array 51 is detected and amplified by a sense amplifier 58 and outputted to input/output pin DQ through data input/output buffer 59.
The SRAM in FIG. 45 has a common input and output pin. Also, redundant circuits such as a row redundancy circuit (row repair circuit) 54 and a column redundancy circuit (a column repair circuit) 57 are provided to enhance the yield.
(2) Detailed structure of respective parts of conventional SRAM
(a) Input buffer circuit (FIG. 46)
FIG. 46 is a circuit diagram illustrating an input buffer circuit of TTL interface used in row address buffer 52, column address buffer 55 and R/W control circuit 62 shown in FIG. 45.
A power-supply potential Vcc is applied to a high potential side power-supply terminal (hereinafter, referred to as a power-supply terminal) and a ground potential GND is applied to a low potential side power-supply terminal (hereinafter, referred to as a ground terminal). In a semiconductor integrated circuit device of TTL interface, the power-supply potential Vcc is set to 5V and the ground potential GND is set to 0V.
In FIG. 46, a CMOS inverter 101 including transistors P1, P2, N1 is connected between an input terminal I1 and a node n1. A CMOS inverter 121 including transistors P61, N61 and a CMOS inverter 123 including transistors P63, N63 are connected between node n1 and an output node O2. A CMOS inverter 122 including transistors P62, N62, a CMOS inverter 124 including transistors P64, N64 and a CMOS inverter 125 including transistors P65, N65 are connected between node n1 and an output node O1.
In the case of TTL interface, an "H" level of an input signal A applied to input terminal I1 is 2.2V and an "L" level is 0.8V. Accordingly, an amplitude of an input signal A is small and the "H" potential is low as compared to a CMOS level ("H"=5V, "L"=0V).
Therefore, it is adjusted so that a logical threshold value of the next stage is 1.5V by CMOS inverter 101. 1.5V is an intermediate potential between 2.2V and 0.8V.
Specifically, a size of transistor N1 is increased. Furthermore, the sizes of transistors N61 and N62 are increased so that logical threshold values of the next stages of CMOS inverters 121 and 122 become 2.5V which is intermediate potential between 5V and 0V.
CMOS inverters 123, 124, 125 work as driver circuits and have a decoder circuit connected to the next stage operate at a high speed.
As shown in FIG. 46, extra one stage of CMOS inverter 125 is required for obtaining complementary output signals B and B in a CMOS circuit.
(b) WE buffer circuit (write enable buffer circuit) (FIGS. 47 and 48)
FIG. 47 is a block diagram illustrating a WE buffer included in the R/W control circuit 62 shown in FIG. 45 and relating parts thereof. FIG. 48 is a waveform diagram for use in describing operation of the WE buffer.
Referring to FIGS. 47 and 48, operation of the SRAM in FIG. 45 will be described. Operation with the worst timing will be considered in which an address signal and an external write enable signal WE change at the same timing (i.e., set up time=0 ns, and hold time=0 ns).
(Period of cycle CY1)
Since a write enable signal WE attains "L" in the cycle CY1, the SRAM comes in a write state. In the write state, it is necessary that a fall of an internal write enable signal IWE is later than switching of a word line.
This is because data is written into a memory cell selected with an address signal An-1 (erroneous writing) if an internal write enable signal IWE falls before switching of word lines.
(Period of cycle Y2)
In cycle CY2, since a write enable signal WE attains "H", a SRAM comes in a read state. In the read state, it is necessary that a rise of an internal write enable signal IWE is earlier than switching of word lines.
This is because it is possible that data is erroneously written into a memory cell selected with an address signal An+1 if an internal write enable signal IWE rises before switching of a word line. This is also because a read time, that is, an access time becomes long since a time when potential of an "L" level of a bit line recovers to a potential close to power-supply potential Vcc in a read state is later than time of switching of word lines.
Accordingly, an internal write enable signal IWE is required to respond slowly to address change coming into a write state and rapidly respond to address change coming into a read state.
On the other hand, an internal output enable signal IOE for controlling an output buffer circuit is required completely opposite characteristics as follows.
(Period of cycle CY1)
If an input pin and an output pin are made common, an input/output pin DQ is used as an input pin in writing operation. Accordingly, it is necessary to bring an output buffer circuit into a disable state to realize high impedance as quickly as possible by raising an internal output enable signal IOE.
(Period of cycle CY2)
On the other hand, in reading operation, when an output buffer circuit is rapidly brought into an enable state with a fall of an internal output enable signal IOE, previous data is once read out and true data is read out thereafter. Accordingly, it has a problem that the access time is long.
Accordingly, an internal output enable signal IOE is required to rapidly respond to address change coming into a write state and slowly respond to address change coming into a read state.
As shown in FIG. 48, a time T11 from a fall point t10 of a write enable signal WE to a fall point of an internal write enable signal IWE is set to be long, and a time T12 from a rise point t11 of a write enable signal WE to a rise point of an internal write enable signal IWE is set to be short.
Furthermore, a time T13 from a fall point t10 of a write enable signal WE to a rise point of an internal output enable signal IOE is set to be short and a time T14 from a rise point t11 of a write enable signal WE to a fall point of an internal output enable signal IOE is set to be long.
As shown in FIG. 47, a WE buffer 18a receives a write enable signal WE and applies the same to a WE waveform shaping circuit 19a and an OE waveform shaping circuit 23a. An internal write enable signal IWE is obtained by WE waveform shaping circuit 19a and an internal output enable signal IOE is obtained by OE waveform shaping circuit 23a. In WE buffer 18a, the input buffer circuit shown in FIG. 46 is used.
(c) Gate circuit (FIGS. 49-51)
FIG. 49 is a circuit diagram showing a CMOS inverter circuit, and FIG. 50 is a circuit diagram showing a BiCMOS gate circuit.
The CMOS inverter circuit shown in FIG. 49 includes a PMOS transistor P66 and an NMOS transistor N66. Transistor P66 is connected between a power-supply terminal and an output terminal O21 and transistor N66 is connected between an output terminal O21 and a ground terminal. Gates of transistors P66 and N66 are connected to an input terminal I21.
The BiCMOS gate circuit shown in FIG. 50 includes a PMOS transistor P13, NMOS transistors N17, N18, N19 and bipolar transistors B7, B8.
Transistor P13 is connected between a power-supply terminal and a node n21, and transistor N17 is connected between node n21 and a ground terminal. Transistor N18 is connected between output terminal O21 and a node n22, and transistor N19 is connected between node n22 and a ground terminal. Gates of transistors P13, N17, N18 are connected to input terminal I21 and a gate of transistor N19 is connected to node n21.
Transistor B7 is connected between a power-supply terminal and output terminal O21, and transistor B8 is connected between output terminal O21 and a ground terminal. A base of transistor B7 is connected to node n21 and a gate of transistor B8 is connected to node n22.
In an MOS LSI, taking compatibility with TTL into account, 5V is used as a power-supply voltage. Also, for the purpose of increasing power-supply noise margin not to degrade performance of MOSFET, and so forth, in an LSI using the design rule larger than 0.8 .mu.m, 5V is used as a power-supply voltage.
When an MOSFET is made fine, an electric field in the vicinity of a drain increases and carriers in a channel are accelerated by the high electric field. Therefore, the carriers get large energy. Such carriers have extremely high energy, so that they are called hot carriers.
At this time, impact ionization occurs to produce electron-hole pairs. These hot carriers are trapped into an oxide film or produce a surface state to degrade characteristics of a transistor. This is called device degradation due to hot carriers.
The impact ionization rate is larger in an NMOS transistor than in a PMOS transistor, and the impurity profile of source and drain is sharp and the electric field in the vicinity of a drain is high. Accordingly, the device degradation due to hot carriers is more serious in an NMOS transistor.
Accordingly, when using the design rule smaller than 0.8 .mu.m for speeding up, some measures must be taken against the device degradation due to hot carriers.
FIG. 51 shows degradation of a MOS transistor due to hot carriers, in which (a) shows a degradation rate of Gm and (b) shows a shift amount of a threshold value. FIGS. 51(a) and (b) are recited in "design of CMOS VLSI", by Editor in Chief; Takuo Sugano and Editor; Tetsuya Iizuka, Baifukan.
It is seen from FIGS. 51(a) and (b) that degradation of the device increases as the drain voltage V.sub.DS increases.
(d) Decoder circuit (FIG. 52)
FIG. 52 is a circuit diagram showing a structure of a decoder circuit used in row decoder 53 and column decoder 56 shown in FIG. 45.
The decoder circuit in FIG. 52 includes four BiNMOS-3NAND circuits 211-214 and four BiCMOS inverters 241-244. Each of BiNMOS-3NAND circuits 211-214 includes PMOS transistors P14-P16, NMOS transistors N20-N25 and a bipolar transistor B23. A structure of each of BiCMOS inverters 241-244 is the same as the structure of the BiCMOS gate circuit shown in FIG. 50.
An input terminal of a corresponding BiCMOS inverter is connected to an output terminal O31 of each BiNMOS-3NAND circuit. Nodes n31 of BiNMOS-3NAND circuits 211-214 and sources of transistors N17 of BiCMOS inverters 241-244 are connected to a ground terminal.
With such a strict design rule as described above, some measures should be taken against hot carriers also in the decoder circuit in FIG. 52.
(e) Output buffer circuit (FIGS. 53-58)
FIG. 53 is a diagram illustrating a general structure of a semiconductor integrated circuit device having a BiCMOS structure outputting a signal of TTL level.
The semiconductor integrated circuit device includes a data generating circuit 340, an output control circuit 350 and an output buffer circuit 300 on one chip. Data generating circuit 340 applies two complementary data signals to output control circuit 350 through data buses DB1, SB2 in response to an external signal. Output control circuit 350 applies a pull-up control signal CTLH and a pull-down control signal CTLL to input terminals I41 and I42 of output buffer circuit 300 in response to an output enable signal OE and a data signal.
Output buffer circuit 300 includes a pull-up circuit 301 and a pull-down circuit 302. Pull-up circuit 301 includes a bipolar transistor B9 connected between a power-supply terminal and an output terminal O41. Pull-down circuit 302 includes an NMOS transistor N67 connected between an output terminal O41 and a ground terminal. A base of transistor B9 is connected to an output terminal I41 and a gate of transistor N67 is connected to input terminal I42.
When a control signal CTLH attains "H", a voltage between base/emitter of transistor B9 increases. Transistor B9 is thus brought into an ON state and output terminal O41 is electrically connected to a power-supply terminal. Accordingly, the potential of output terminal O41 rises to "H".
On the other hand, when a control signal CTLL attains "H", transistor N67 comes into an ON state. Output terminal O41 is thus electrically connected to a ground terminal. Accordingly, the potential of output terminal O41 falls to "L".
Another example of pull-up circuit 301 is shown in FIG. 54. The pull-up circuit 301 of FIG. 54(a) includes a bipolar transistor B9 and a diode D6 connected in series between a power-supply terminal and an output terminal O41. A control signal CTLH is applied to a base of transistor B9.
The pull-up circuit 301 of FIG. 54(b) includes an NMOS transistor N68 connected between a power-supply terminal and an output terminal O41. A control signal CTLH is applied to a gate of transistor N68.
The pull-up circuit 301 of FIG. 54(c) includes a PMOS transistor P67 connected between a power-supply terminal and an output terminal O41. A control signal CTLH is applied to a gate of transistor P67.
In the pull-up circuits 301 of FIGS. 54(a), (b), when a control signal CTLH attains "H", transistors B9, N68 and diode D6 turn on and the potential of output terminal O41 rises to "H". Also, in the pull-up circuit 301 of FIG. 54(c), when a control signal CTLH attains "L", transistor P67 turns on and the potential of output terminal O41 rises to "H".
Another example of pull-down circuit 302 is shown in FIG. 55.
The pull-down circuit 302 of FIG. 55(a) includes NMOS transistors N31, N69 connected in series between an output terminal O41 and a ground terminal, and a bipolar transistor B10 connected in parallel to these transistors N31, N69.
A control signal CTLL is applied to a gate of transistor N31 and a gate of transistor N69 is connected to output terminal O41. Potential of a connection point of transistors N31, N69 is applied to a base of transistor B10.
When the potential of output terminal O41 is "H", transistor N69 turns on. Base potential of transistor B10 thus attains "L", and output terminal O41 is charged by the pull-up circuit.
When a control signal CTLL attains "H" at this time, transistor N31 turns on and the charge of output terminal O41 is supplied to the base of transistor B10. As a result, transistor B10 turns on and output terminal O41 is electrically connected to the ground terminal. Accordingly, the potential of output terminal O41 attains "L".
In the pull-down circuit 302 of FIG. 55(b), a resistor R2 is connected in place of transistor N69 shown in FIG. 55(a). Also in the pull-down circuit 302, a control signal CTLL attains "H" to bring the potential of output terminal O41 to "L".
In the pull-down circuit 302 of FIG. 55(a), when the potential of output terminal O41 is at "H", transistor N69 comes in an ON state and the base of transistor B10 is electrically connected to the ground terminal. Accordingly, even if current leaks to the base of transistor B10 because of some reason from transistor N31 to be in an OFF state in such a period, the leak current is discharged through transistor N69.
Accordingly, it is avoided that transistor B10 somewhat reaches an ON state due to such leak current to cause throughout current to flow from the power-supply terminal to the ground terminal through the pull-up circuit and transistor B10.
Similarly, in the pull-down circuit 302 of FIG. 55(b), leak current of transistor N31 is prevented from being supplied to the base of transistor B10 by resistor R2. Accordingly, generation of throughout current in a period in which the potential of output terminal O41 is at "H" can be avoided.
Examples of output control circuit 350 are shown in FIGS. 56 and 57.
The output control circuit 350 of FIG. 56(a) includes conversion input type 2-input AND gates 351 and 352. If an output enable signal OE is at "L", levels of control signals CTLH and CTLL are determined by potentials of data buses DB1 and DB2, respectively.
If potentials of data buses DB1, DB2 are at "L" and "H", respectively, control signals CTLH and CTLL respectively attain "H" and "L". On the other hand, if potentials of data buses DB1 and DB2 are respectively at "H" and "L", control signals CTLH and CTLL attain "L" and "H", respectively.
Accordingly, when a data signal of "L" corresponding to a logical value "0" is applied to data bus DB2 by a data generating circuit, the potential of output terminal O41 attains "L". On the contrary, when a data signal of "H" corresponding to a logical value "1" is applied to data bus DB2 by the data generating circuit, the potential of output terminal O41 attains "H". That is, a data signal applied to data bus DB2 from the data generating circuit is outputted at output terminal O41.
The output control circuit 350 of FIG. 56(b) includes input conversion type 2-input AND gates 351 and 352 and an inverter 353. The output control circuit 350 is connected to a single data bus DB. In a period in which an output enable signal OE is at "L", a data signal applied from the data generating circuit to the data bus DB is outputted at output terminal O41.
The output control circuit 350 of FIG. 57 includes a 2-input NAND gate 354, an input conversion type 2-input AND gate 352 and an inverter 355. When an output enable signal OE is at "L", potentials of control signals CTLH and CTLL are both determined by the potential of data bus DB.
If the potential of data bus DB is "H", both of control signals CTLH and CTLL attain "L". On the contrary, if the potential of data bus DB is "L", control signals CTLH and CTLL both attain "H".
Accordingly, when a data signal of "H" is applied to data bus DB from the data generating circuit, a transistor P67 of output buffer circuit 300 turns on and a transistor N67 turns off. As a result, a data signal of "H" is outputted at output terminal O41. Similarly, if a data signal of "L" is applied to data bus DB from the data generating circuit, transistor P67 of output buffer circuit 300 turns off and transistor N67 turns on. A data signal of "L" is thus outputted at output terminal O41.
An output enable signal OE is a signal for instructing as to whether a data signal generated by the data generating circuit is to be externally outputted or not. In the output control circuit 350 of FIGS. 56(a), (b), if an output enable signal OE is at "H", both of control signals CTLH and CTLL attain "L". Accordingly, transistors B9 and N67 of output buffer circuit 300 turn off and output impedance of output terminal O41 increases.
If an output enable signal OE is "H" in the output control circuit 350 of FIG. 57, a control signal CTLH attains "H" and a control signal CTLL attains "L". Therefore, transistors P67 and N67 of output buffer circuit 300 turn off and the output impedance of output terminal O41 increases.
FIG. 58 is a circuit diagram illustrating a structure of an output buffer circuit used in the data input/output buffer 59 shown in FIG. 45.
The output buffer circuit includes a CMOS inverter 360 having transistors P68 and N70, a CMOS.cndot.2NOR circuit 370 having transistors P69, P70, N71, N72, a CMOS.cndot.2NOR circuit 380 having transistors P71, P72, N73, N74 and a BiNMOS driver circuit 300 having transistors B9, N67.
An input signal SA is applied to input terminal 150. The output buffer circuit comes into an output enable state (read state) when a chip select signal CS is at "L", and comes in an output disable state (write state) or a chip non-selection state when a chip select signal CS is at "H". In the output disable state or the chip non-selection state, output terminal O50 attains a high impedance state. In the output buffer circuit, a rise of an output signal is speeded up by bipolar transistor B9.
(f) Bit line load circuit (FIGS. 59-63)
FIG. 59 is a diagram showing memory cell array 51 shown in FIG. 45 and a structure in the vicinity thereof.
A plurality of word lines WLs and a plurality of bit line pairs BLs, BLs are arranged intersecting one another and memory cells MCs are provided at their intersections.
Each memory cell MC has a structure shown in FIG. 60(a) or (b), for example. The memory cell of FIG. 60(a) includes NMOS transistors N75-N78 and load resistors R6, R7. The memory cell of FIG. 60(b) includes PMOS transistors P73 and P74 and NMOS transistors N75-N78.
In FIG. 59, a bit line load circuit 470 and a column selection circuit 480 are connected to each of bit line pairs BL, BL. Bit line load circuit 470 is connected to write data buses WBa, WBb. Column selection circuit 480 is connected to read data buses RBa and RBb. A write driver 490 is connected to write data buses WBa and WBb and a sense amplifier 420 is connected to read data buses RBa and RBb.
Bit line load circuit 470 is controlled with a signal obtained by a logical product of a column selection signal Yi (i=1 through n) and a write enable signal WE. Column selection circuit 480 is controlled by a column selection signal Yi. Column selection circuit 480 transmits potential difference occurring in bit lines BL, BL to read data buses RBa and RBb. Sense amplifier 420 amplifies signals of read data buses RBa and RBb and applies the same to an output circuit.
FIG. 61 shows waveforms of bit line potential when a SRAM changes from a write state to a read state by change of an external write enable signal WE from "L" to "H".
In FIG. 61, a simultaneous change of a write enable signal WE and an external address signal is shown. It is now assumed that a column address signal is fixed and only a row address signal changes.
In writing operation, potential of one of bit line pair BL, BL is decreased to a write level. Writing operation is finished with a write enable signal WE being rising, and bit lines are charged by bit line load circuit 470.
In FIG. 61, the solid line L5 indicates bit line potential when bit lines are rapidly charged and normal operation is performed. If charging of bit lines after writing operation is finished is late with respect to switching of word lines, as shown by the broken line L6 in FIG. 61, the crossing of bit line potentials is late to cause a delay of access, or erroneous writing may occur as shown in the broken line L7.
Detailed circuit structure of a bit line load circuit is shown in FIGS. 62 and 63.
The bit line load circuit of FIG. 62 includes an equalize transistor P28, pull-up transistors P29, P30, and transfer gate transistors N47, N48 for transmitting signals of data buses WBa and WBb to bit line pair BL, BL.
A signal Yi.cndot.WE obtained by logical product of a column selection signal and a write enable signal is applied to input terminal I61.
In reading operation, signal Yi.cndot.WE is at "L". Therefore, transistors P28-P30 turn on and transistors N47, N48 turn off. With cell current of a selected memory cell flowing to transistors P28-P30, potential difference is caused between bit lines BL, BL. The potential difference is transmitted to read data buses RBa, RBb through the column selection circuit 480 of FIG. 59. Equalize transistor P28 acts to limit an amplitude of bit line potential.
In writing operation, a signal Yi.cndot.WE is at "H". Therefore transistors P28-P30 turn off and transistors N47 and N48 turn on. Potential of one of write data buses WBa and WBb attains "L" and the data of the write data bus is transferred to bit line BL or BL through transistor N47 or N48. At this time, transistors P28-P30 are OFF, so that write current does not flow to the bit line load circuit.
When writing operation is finished, potentials of write data buses WBa and WBb both attain "H". Bit lines of "L" are charged by write driver 490 of FIG. 59 through transistor N47 or N48. Also, with the end of writing operation, a signal Yi.cndot.WE changes to "L". Transistors P28-P30 thus turn on and bit lines are also charged by these transistors P28-P30.
In the bit line load circuit of FIG. 63, instead of pull-up transistors P29, P30 shown in FIG. 62, pull-up transistors N79 and N80 are provided.
In reading operation, a signal Yi.cndot.WE is at "L". Accordingly, transistor P28 is ON and transistors N47 and N48 are OFF. With cell current of a selected memory cell flowing to transistors P28, N79, N80, a potential difference is caused between bit lines BL and BL. The potential difference is transferred to read data buses RBa and RBb through the column selection circuit 480 of FIG. 59.
In writing operation, a signal Yi.cndot.WE is at "H". Therefore, transistor P28 is OFF and transistors N47 and N48 are ON. Potential of one of write data buses WBa and WBb attains "L", and data of that data bus is transmitted to bit line BL or BL through transistor N47 or N48. At this time, although transistor P28 is OFF, transistors N79 and N80 are ON. Accordingly, write current flows to the bit line load circuit.
When writing operation is finished, potentials of write data buses WBa and WBb both attain "H". Bit lines which attain "L" are charged by write driver 490 of FIG. 59 through transistor N79 or N80 and transistor N47 or N48. Also, with the end of writing operation, a signal Yi.cndot.WE changes to "L". Accordingly, that bit line is also charged by transistor P28.
(g) Chip layout (FIGS. 64-66)
FIGS. 64 and 65 show pin arrangement of 32KX8 TTL SRAM. FIG. 64 shows an example of corner power pin arrangement and FIG. 65 shows an example of dual center power pin arrangement.
In the corner power pin arrangement of FIG. 64, a GND pin and a VCC pin are respectively assigned to a fourteenth pin and a twenty-eighth pin at corners of the package. In the dual center power pin arrangement of FIG. 65, GND pins are assigned to the ninth pin and the twenty-fifth pin, and VCC pins are assigned to the eighth pin and the twenty-fourth pin.
The SRAMs of FIGS. 64 and 65 operate completely the same except for the pin arrangements.
Such a corner power pin arrangement has been often used in general SRAMs in conventional cases. However, in the center power pin arrangement, since power-supply pins such as GND pin and VCC pin are arranged in the center of the package, the length of power-supply interconnection is short and impedance component of power-supply interconnection is small, including interconnection of the frame of package and interconnection inside the chip. Therefore, the center power pin arrangement has a feature that it can suppress a voltage decrease of power-supply interconnection and output noise.
Therefore, use of center power pin arrangement as shown in FIG. 65 is on an increase these days mainly in high-speed SRAMs of multi-bits having a large capacity of 256K bits or more.
FIG. 66 is a diagram showing layout of the entirety of a chip of a SRAM using the center power pin arrangement.
The SRAM of FIG. 66 is a SRAM of the X4 structure including four output circuits 291a-294a. Memory cell arrays 1a and 1b are arranged on a chip CH and a global row decoder 4 of a division word line structure is arranged in a central portion of the chip CH.
Bit line load circuits 471 and 472 are each arranged on one side of each memory cell array 1a and 1b and column selection circuits 481 and 482 and sense amplifiers 421 and 422 are arranged on each of the other sides of memory cell arrays 1a and 1b.
In the center power pin arrangement, output pins are provided on both sides of a power-supply pin, so that output circuits 291a and 292a are arranged on one side portion of memory cell arrays 1a and 1b, and output circuits 293a and 294a are arranged on the other side portion of memory cell arrays 1a and 1b.
Read data buses RB1-RB4 are arranged on one side portion on the chip CH. Data read from memory cell arrays 1a and 1b are amplified by sense amplifiers 421 and 422, and transmitted to output circuits 291a-294a through read data buses RB1-RB4.
(h) Shift redundancy circuits (FIGS. 67-69)
A redundancy circuit is used for preventing a decrease of yield by replacing defective bits by spare bits. With an increase of capacity of RAM, it is becoming an important problem what redundancy system should be introduced.
A conceptual diagram of the shift redundancy system is shown in FIG. 67. The shift redundancy system is a method in which defective bits are sequentially replaced by adjacent bits by turning a switch provided in the middle of a decode path.
Normally, outputs D1-D4 of column decoder 450 are respectively connected to columns C1-C4 by switches S1-S4 of a column redundancy control circuit SW0. Each column includes a set of bit line pair and a plurality of memory cells connected thereto. If, as shown in FIG. 67, a defective bit exists in the second column C2 from left, outputs D2-D4 are respectively connected to columns C3, C4 and a redundant column RC1 by turning switches S2-S4.
FIG. 68 is a circuit diagram illustrating a detailed structure of the shift redundancy system of FIG. 67.
If fuses F1-F3, FE are in a connected state, transistor N60 is OFF. Accordingly, decoder outputs D1, D2, D3 are respectively connected to columns C1, C2, C3. Disconnecting only fuses F2, FE, decoder output D1 is connected to column C1 and decoder outputs D2, D3 are respectively connected to columns C3, C4.
Thus, the shift redundancy system has two features as follows. One is that a program circuit of a redundancy circuit is extremely simple. Another one is that a delay of access does not occur at all even if a defective bit is replaced since a selected path does not change.
FIG. 69 is a diagram illustrating one example of a global row decoder including a shift redundancy circuit.
As shown in FIG. 66, if a global row decoder 4 is provided in a center portion of a chip CH, global word lines exist on left and right sides of global row decoder 4.
In FIG. 69, row redundancy control circuit 50 includes a switch circuit SW10 including switches S11-S13. Outputs of global row decoder 4 are respectively connected to left global word lines WL1-WL3 and right global word lines WR-WR3 through switches S11-S13.
For example, if a defect exists in the third global word line WL3 from left, switch S13 is switched to the side of redundant global word lines REL, RER. The third global word lines WL3 and WR3 are thus replaced by redundant global word lines REL and RER.
(3) Recitation of prior art literatures
(a) Input buffer circuit
Japanese Patent Laying-Open No. 60-142618, Japanese Patent Laying-Open No. 62-230221 and Japanese Patent Laying-Open No. 2-237313 disclose input buffer circuits in which speed up is attempted by substantially removing difference in delay time between a non-inverted signal and an inverted signal.
(b) Output buffer circuit
Japanese Patent Laying-Open No. 60-68718 discloses an output buffer circuit shown in FIG. 58 of the present application.
Japanese Patent Laying-Open No. 61-125222 discloses a technique of turning on a plurality of output transistors with time delay.
Japanese Patent Laying-Open No. 62-48806 discloses an output buffer circuit in which timings of turn-off of respective transistors in a first circuit and a second circuit are simultaneous and having different amounts of delay to slightly deviate timings of turn-on.
(c) Bit line load circuit
R. A. Kertis et al., "A 12-ns ECL I/O 256KX1-bit SRAM Using a 1-.mu.m BiCMOS Technology", IEEE J. Solid-State Circuits, vol. 23, No. 5, pp. 1048-1053, October 1988 discloses to use bipolar in bit line load and charge write bit lines at high speed.
(d) Architecture of semiconductor integrated circuit device
Japanese Patent Laying-Open No. 61-283162 and Japanese Patent Laying-Open No. 2-2668 (U.S. Pat. No. 4,982,372) disclose to arrange a plurality of decoders on both sides of a memory array block, connect decoders on one side to every other selection lines and connect decoders on the other side to the remaining alternative selection lines.
(e) Redundancy circuit
Japanese Patent Publication No. 61-35636, Japanese Patent Laying-Open No. 61-61300 and Japanese Patent Application No. 1-142450 (corresponding U.S. application Ser. No. 500,965) disclose shift redundancies.
Japanese Patent Laying-Open No. 62-250600 discloses to arrange redundancy control circuits on left and write of a decoder.
A. Ohba et al., "A 7-ns 1-Mb BiCMOS ECL SRAM with Shift Redundancy", IEEE J. Solid-State Circuits, vol. 26, No. 4, pp. 507-512, April 1991 discloses a SRAM in which a shift redundancy is used.
(f) Japanese Patent Laying-Open No. 60-170090 discloses a BiCMOS SRAM.
(4) Problems to be solved by the Invention
(a) Input buffer circuit
In the input buffer circuit shown in FIG. 46, complementary outputs with the same speed cannot be obtained because an output signal B delays from an output signal B by one stage of CMOS inverter.
Accordingly, it has a problem that multiselection is likely to be caused in the next stage of decoder circuit. It is possible that erroneous writing may be applied to a non-selection memory cell, or erroneous read may be applied to a non-selection memory cell due to such multiselection.
(b) WE buffer circuit
In the structure shown in FIG. 47, it is necessary to separately waveform-shape an output signal of WE buffer 18a by WE waveform shaping circuit 19a and OE waveform shaping circuit 23a in order to obtain an internal write enable signal IWE and an internal output enable signal IOE with the timings shown in FIG. 48.
If an internal write enable signal which responds slowly to address change coming into a write state and responds quickly to address change coming into a read state, and an internal output enable signal which responds quickly to address change coming into a write state and responds slowly to address change coming into a read state can be simultaneously realized, the operation speed can be increased.
(c) Gate circuit
If the design rule becomes strict for speed up in the BiCMOS gate circuit or the BiNMOS gate circuit shown in FIG. 50, some measures must be taken for the hot carriers.
(d) Decoder circuit
In the decoder circuit shown in FIG. 52, if the design rule becomes strict for speed up, some measures must be taken for hot carriers.
(e) Output buffer circuit
In the output buffer circuits 300 shown in FIGS. 53 through 58, in order to quicken a fall of an output signal of output terminal O41, it is necessary to increase the current driving capability of transistors of pull-down circuit 302.
In output buffer circuits shown in FIGS. 53, 56(a) and (b), 57 and 58, an increase of size of NMOS transistor N67 can increase the current driving capability. In the pull-down circuit 302 shown in FIGS. 55(a) and (b), the current driving capability can be increased by increasing the size of NMOS transistor N31 and increasing collector current of bipolar transistor B10.
An increase in current driving capability of transistors of pull-down circuit 302, however, causes rapid change of potential of output terminal O41, resulting in so-called ringing in which potential of output terminal O41 or the ground terminal fluctuates about a ground potential (approximately 0V). Such ringing may cause malfunction of other circuits which are to always receive ground potential.
Furthermore, a time required until the potential of output terminal O41 is stabilized at ground potential becomes long, so that an access time for the semiconductor integrated circuit device is increased.
Furthermore, an increase in the size of a NMOS transistor increases charge/discharge current flowing in the transistor when gate potential of that transistor changes. As a result, a signal transmission time of NMOS transistor increases.
Since current driving capability of a bipolar transistor is larger than current driving capability of MOS transistor, according to the pull-down circuit 302 shown in FIGS. 55(a) and (b), it is possible to enhance a falling speed of an output signal without largely increasing the size of NMOS transistor N31. Accordingly, the degradation of operation velocity due to an increase in charge/discharge current of NMOS transistor can be suppressed.
However, in the pull-down circuit 302 shown in FIGS. 55(a) and (b), when the potential of output terminal O41 is at "L", the NMOS transistor N31 is ON. Accordingly, a base and a collector of bipolar transistor B10 are electrically connected. Accordingly, it results in a PN diode equivalently connected between output terminal O41 and the ground terminal. Therefore, the potential of output terminal O41 becomes higher than 0V depending on the magnitude of current flowing through bipolar transistor B10 from output terminal O41 to the ground terminal. For example, if current of 8 mA flows to bipolar transistor B10, base/emitter voltage of bipolar transistor B10 becomes 0.8V. Accordingly, the potential of output terminal O41 becomes 0.8V.
In a SRAM of which input/output signals are of TTL level, output potential of an output buffer circuit driving output current of 8 mA must be equal to or lower than 0.4V. Therefore, in a TTL SRAM in which the pull-down circuit 302 of FIGS. 55(a) and (b) are used, data can be outputted at high speed, but such standard cannot be satisfied.
(f) Bit line load circuit
In the bit line load circuit shown in FIG. 62, since pull-up transistors P29 and P30 turn off in writing operation, write current does not flow. However, since bit lines are charged through pull-up transistors P29, P30 controlled by a signal Yi.cndot.WE after the writing operation is finished, the velocity of charging bit lines is low.
In the bit line load circuit shown in FIG. 63, since pull-up transistors N79 and N80 do not turn off in writing operation, the velocity of charging bit lines after the end of writing operation is high. However, a large writing current flows in writing operation.
(g) Chip layout
In the chip layout shown in FIG. 66, it is necessary to connect read data buses RB1 and RB2 provided on the other side of memory cell arrays 1a and 1b to output circuits 291a and 292a provided on one side of memory cell arrays 1a and 1b. Therefore, read data buses RB1 and RB2 are longer than read data buses RB3 and RB4 by a length of memory cell arrays 1a and 1b in the bit line direction. As a result, a delay occurs in accessing.
(h) Shift redundancy circuit
In the shift redundancy circuit shown in FIG. 67, defects of continuous two bits cannot be repaired. Defects of continuing two bits occur when a defect occurs over two memory cells. Such a defect relatively often occurs, so that a repairing rate is largely affected by whether a 2-bit defect can be made up or not.
In the shift redundancy circuit shown in FIG. 69, for example, when defects occur in the left third global word line WL3 and the right second global word line WR2, both of such defects cannot be repaired.
A redundancy system is desired in which defects in a left global word line and a right global word line can be separately repaired without increasing the number of redundant global word lines.